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» Dimensionality reduction and generalization
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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
ICCD
2002
IEEE
152views Hardware» more  ICCD 2002»
16 years 3 months ago
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 3 months ago
State re-encoding for peak current minimization
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
ICCAD
2006
IEEE
150views Hardware» more  ICCAD 2006»
16 years 3 months ago
Conjoining soft-core FPGA processors
Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-po...
David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. ...
ICCAD
2006
IEEE
122views Hardware» more  ICCAD 2006»
16 years 3 months ago
Network coding for routability improvement in VLSI
With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links....
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulat...