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» Dimensionality reduction and generalization
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GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
16 years 9 days ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
IPPS
2005
IEEE
16 years 9 days ago
A Robust Interference Model for Wireless Ad-Hoc Networks
Among the foremost goals of topology control in wireless ad-hoc networks is interference reduction. This paper presents a receiver-centric interference model featuring two main ad...
Pascal von Rickenbach, Stefan Schmid, Roger Watten...
CIKM
2005
Springer
16 years 7 days ago
Joint deduplication of multiple record types in relational data
Record deduplication is the task of merging database records that refer to the same underlying entity. In relational databases, accurate deduplication for records of one type is o...
Aron Culotta, Andrew McCallum
FPGA
2004
ACM
136views FPGA» more  FPGA 2004»
16 years 2 days ago
Active leakage power optimization for FPGAs
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
Jason Helge Anderson, Farid N. Najm, Tim Tuan
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CODES
2003
IEEE
16 years 2 hour ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid