Sciweavers

3006 search results - page 291 / 602
» Dimensionality reduction and generalization
Sort
View
ASIACRYPT
2005
Springer
16 years 9 days ago
Gate Evaluation Secret Sharing and Secure One-Round Two-Party Computation
We propose Gate Evaluation Secret Sharing (GESS) – a new kind of secret sharing, designed for use in secure function evaluation (SFE) with minimal interaction. The resulting simp...
Vladimir Kolesnikov
GLVLSI
2010
IEEE
138views VLSI» more  GLVLSI 2010»
15 years 12 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
Emre Salman, Eby G. Friedman
VLSID
2002
IEEE
81views VLSI» more  VLSID 2002»
15 years 11 months ago
A New Synthesis of Symmetric Functions
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattac...
AI
2001
Springer
15 years 11 months ago
The Bottom-Up Freezing: An Approach to Neural Engineering
This paper presents a new pruning method to determine a nearly optimum multi-layer neural network structure. The aim of the proposed method is to reduce the size of the network by ...
Ali Farzan, Ali A. Ghorbani
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
15 years 11 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar