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» Dimensionality reduction and generalization
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GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 11 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...
RTA
2010
Springer
15 years 10 months ago
Infinitary Rewriting: Foundations Revisited
Infinitary Term Rewriting allows to express infinitary terms and infinitary reductions that converge to them. As their notion of transfinite reduction in general, and as binary...
Stefan Kahrs
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
VTC
2010
IEEE
116views Communications» more  VTC 2010»
15 years 5 months ago
Downlink Transmission in Multi-Carrier Systems with Reduced Feedback
— in this paper we address the problem of reducing the feedback for the downlink transmission in multi-carrier systems. In these systems multiple Component Carriers (CCs) are agg...
Yuanye Wang, Klaus I. Pedersen, Troels B. Sø...