3006 search results - page 237 / 602 » Dimensionality reduction and generalization |
122
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual rout...
178
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
193
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NOSSDAV
2009
Springer
16 years 1 months ago
2009
Springer
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
167
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GLVLSI
2008
IEEE
16 years 1 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
144
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ISLPED
2003
ACM
15 years 12 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...