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» Digital System Design: Architectures, Methods and Tools
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ASPDAC
2001
ACM
83views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
Tony Givargis, Frank Vahid, Jörg Henkel
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 11 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 10 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
SPIESR
2004
127views Database» more  SPIESR 2004»
15 years 7 months ago
New perspective on visual information retrieval
Visual information retrieval (VIR) is a research area with more than 300 scientific publications every year. Technological progress lets surveys become out of date within a short ...
Horst Eidenberger
EAGC
2003
Springer
15 years 11 months ago
Automatic Services Discovery, Monitoring and Visualization of Grid Environments: The MapCenter Approach
The complexity of Grid environments is growing as more projects and applications appear in this quick-evolving domain. Widespread applications are distributed over thousands of com...
Franck Bonnassieux, Robert Harakaly, Pascale Prime...