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DAC
1997
ACM
15 years 11 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
15 years 11 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
EURASIP
1990
15 years 11 months ago
Inversion in Time
Inversionof multilayersynchronous networks is a method which tries to answer questions like What kind of input will give a desired output?" or Is it possible to get a desired...
Sebastian Thrun, Alexander Linden
200
Voted
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
15 years 11 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
220
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CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
15 years 11 months ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli