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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
16 years 26 days ago
A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's
— The accuracy of high-speed DAC’s is limited by dynamic effects such as glitches. Here, a digital calibration technique to compensate this effect is presented. Because of the ...
B. Catteau, Pieter Rombouts, Ludo Weyten
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
15 years 11 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
15 years 11 months ago
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
Amir Attarha, Mehrdad Nourani
ICASSP
2011
IEEE
14 years 10 months ago
Learning sparse dictionaries with a popularity-based model
Sparse signal representation based on overcomplete dictionaries has recently been extensively investigated, rendering the state-of-the-art results in signal, image and video proce...
Jianzhou Feng, Li Song, Xiaoming Huo, Xiaokang Yan...
ISCAS
2006
IEEE
85views Hardware» more  ISCAS 2006»
16 years 18 days ago
Digital phase-shift modulation for an isolation buffer in silicon-on-sapphire CMOS
— We designed and fabricated a 4-channels digital isolation amplifier in a 0.5µm Silicon-on-Sapphire technology. The isolation device was fabricated on a single die, taking adv...
Eugenio Culurciello, Philippe O. Pouliquen, Andrea...