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GLVLSI
2008
IEEE
105views VLSI» more  GLVLSI 2008»
15 years 7 months ago
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ICASSP
2011
IEEE
14 years 10 months ago
Adjugate pairs of sparse arrays for sampling two dimensional signals
Sparse sampling with coprime lattice arrays was introduced recently in the literature. It has been shown that a dense coarray can be constructed from such a pair of arrays, and is...
Palghat P. Vaidyanathan, Piya Pal
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
15 years 11 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 11 months ago
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices
Behavioral models of digital devices based on Radial Basis Functions (RBF) are incorporated into a Finite-Difference Time-Domain (FDTD) solver for full-wave analysis of interconne...
Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. ...
ICASSP
2009
IEEE
16 years 1 months ago
Compressive spectral estimation for nonstationary random processes
We propose a “compressive” estimator of the Wigner-Ville spectrum (WVS) for time-frequency sparse, underspread, nonstationary random processes. A novel WVS estimator involving...
Alexander Jung, Georg Tauböck, Franz Hlawatsc...