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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 1 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
174
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SPAA
2010
ACM
15 years 11 months ago
Online capacity maximization in wireless networks
In this paper we study a dynamic version of capacity maximization in the physical model of wireless communication. In our model, requests for connections between pairs of points i...
Alexander Fanghänel, Sascha Geulen, Martin Ho...
CF
2009
ACM
15 years 11 months ago
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors
Energy consumption and heat dissipation have become key considerations for modern high performance computer systems. In this paper, we focus on non-clairvoyant speed scaling to mi...
Hongyang Sun, Yangjie Cao, Wen-Jing Hsu
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
15 years 8 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...