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166
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
178
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PATMOS
2004
Springer
16 years 13 days ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
178
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CHI
2010
ACM
15 years 12 months ago
2010
ACM
Establishing a grassroots innovation pipeline has come to the fore as strategy for nurturing innovation within large organizations. A key element of such pipelines is the use of a...
167
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TCAD
2002
15 years 6 months ago
2002
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
200
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SIGMETRICS
2008
ACM
15 years 7 months ago
2008
ACM
In this paper, we discuss recent work on buffer sizing in the context of an ISP's need to offer and guarantee competitive Service Level Agreements (SLAs) to its customers. Si...