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ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
16 years 1 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...
192
Voted
IPPS
2005
IEEE
16 years 1 months ago
WSPeer - An Interface to Web Service Hosting and Invocation
— This paper introduces WSPeer, a high level interface to hosting and invoking Web services. WSPeer aims to support the diversification of Web service deployments by providing a...
Andrew Harrison, Ian J. Taylor
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
16 years 21 days ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
176
Voted
HICSS
2002
IEEE
99views Biometrics» more  HICSS 2002»
16 years 11 days ago
Privacy in Distributed Electronic Commerce
In recent years there has been a movement toward deployment of distributed approaches for electronic commerce. Intelligent software agents, for instance, may be instructed to act ...
Larry Korba
ICS
1999
Tsinghua U.
15 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer