Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
— This paper introduces WSPeer, a high level interface to hosting and invoking Web services. WSPeer aims to support the diversification of Web service deployments by providing a...
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
In recent years there has been a movement toward deployment of distributed approaches for electronic commerce. Intelligent software agents, for instance, may be instructed to act ...
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...