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ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
16 years 1 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ISORC
2008
IEEE
16 years 1 months ago
Usability Aspects of WCET Analysis
Knowing the program timing characteristics is fundamental to the successful design and execution of real-time systems. A critical timing measure is the worst-case execution time (...
Jan Gustafsson
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
16 years 1 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
DSN
2007
IEEE
16 years 1 months ago
Assessing Robustness of Web-Services Infrastructures
Web-services are supported by a complex software infrastructure that must provide a robust service to the client applications. This practical experience report presents a practica...
Marco Vieira, Nuno Laranjeiro, Henrique Madeira
GLOBECOM
2007
IEEE
16 years 1 months ago
Process for QoS-Aware IP Network Planning Using Accounting Data and Effective Bandwidth Estimation
- In this paper we describe QoSPlan – a generalized process for preparing information relevant to QoS-aware IP network planning. QoSPlan is designed to reduce the cost of deploym...
Alan Davy, Dmitri Botvich, Brendan Jennings