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ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
16 years 1 days ago
Maximal Causality Analysis
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algo...
Klaus Schneider, Jens Brandt, Tobias Schüle, ...
EDCC
2005
Springer
15 years 12 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...
VLSI
2005
Springer
15 years 12 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
VMCAI
2005
Springer
15 years 12 months ago
Information Flow Analysis for Java Bytecode
Abstract. We present a context-sensitive compositional analysis of information flow for full (mono-threaded) Java bytecode. Our idea consists in transforming the Java bytecode int...
Samir Genaim, Fausto Spoto
APN
2004
Springer
15 years 11 months ago
Reachability Set Generation for Petri Nets: Can Brute Force Be Smart?
Generating the reachability set is one of the most commonly required step when analyzing the logical or stochastic behavior of a system modeled with Petri nets. Traditional “expl...
Gianfranco Ciardo