The standard translation of a Bounded Model Checking (BMC) instance into a satisfiability problem, (a.k.a SAT), might produce misleading results in the case when the model under v...
Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Ra...
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Logic languages based on the theory of rational, possibly infinite, trees have much appeal in that rational trees allow for faster unification (due to the safe omission of the occ...
Roberto Bagnara, Roberta Gori, Patricia M. Hill, E...
Background: There are many fewer genes in the human genome than there are expressed transcripts. Alternative splicing is the reason. Alternatively spliced transcripts are often sp...
Ari B. Kahn, Michael C. Ryan, Hongfang Liu, Barry ...
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...