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» Deviation Analysis: A New Use of Model Checking
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ENTCS
2006
103views more  ENTCS 2006»
15 years 6 months ago
Supporting SAT based BMC on Finite Path Models
The standard translation of a Bounded Model Checking (BMC) instance into a satisfiability problem, (a.k.a SAT), might produce misleading results in the case when the model under v...
Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Ra...
QEST
2006
IEEE
16 years 15 days ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
CORR
2004
Springer
151views Education» more  CORR 2004»
15 years 6 months ago
Finite-Tree Analysis for Constraint Logic-Based Languages: The Complete Unabridged Version
Logic languages based on the theory of rational, possibly infinite, trees have much appeal in that rational trees allow for faster unification (due to the safe omission of the occ...
Roberto Bagnara, Roberta Gori, Patricia M. Hill, E...
BMCBI
2007
115views more  BMCBI 2007»
15 years 6 months ago
SpliceMiner: a high-throughput database implementation of the NCBI Evidence Viewer for microarray splice variant analysis
Background: There are many fewer genes in the human genome than there are expressed transcripts. Alternative splicing is the reason. Alternatively spliced transcripts are often sp...
Ari B. Kahn, Michael C. Ryan, Hongfang Liu, Barry ...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
16 years 3 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap