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ASAP
2002
IEEE
76views Hardware» more  ASAP 2002»
15 years 11 months ago
A Component Architecture for FPGA-Based, DSP System Design
† Introducing FPGA components into DSP system implementations creates an assortment of challenges across system architecture and logic design. Recognizing that some of the greate...
Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakaji...
CCS
2006
ACM
15 years 10 months ago
TinySeRSync: secure and resilient time synchronization in wireless sensor networks
Accurate and synchronized time is crucial in many sensor network applications due to the need for consistent distributed sensing and coordination. In hostile environments where an...
Kun Sun, Peng Ning, Cliff Wang
ACL
2010
15 years 4 months ago
WebLicht: Web-Based LRT Services for German
This software demonstration presents WebLicht (short for: Web-Based Linguistic Chaining Tool), a webbased service environment for the integration and use of language resources and...
Erhard W. Hinrichs, Marie Hinrichs, Thomas Zastrow
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
16 years 7 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
ICS
2009
Tsinghua U.
16 years 1 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron