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HPCA
2002
IEEE
16 years 6 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
16 years 1 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
CVPR
2007
IEEE
16 years 27 days ago
Surveillance in Virtual Reality: System Design and Multi-Camera Control
This paper advocates a Virtual Vision paradigm and demonstrates its usefulness in camera sensor network research. Virtual vision prescribes the use of a visually and behaviorally ...
Faisal Qureshi, Demetri Terzopoulos
IPPS
2007
IEEE
16 years 25 days ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
16 years 18 days ago
A Field Programmable RFID Tag and Associated Design Flow
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...