Sciweavers

3395 search results - page 154 / 679
» Designs, Disputes and Strategies
Sort
View
DATE
2005
IEEE
235views Hardware» more  DATE 2005»
16 years 3 days ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
IWSSD
2000
IEEE
15 years 11 months ago
Design Guidance through the Controlled Application of Constraints
We seek to facilitate development of high quality software designs and architectures by using rigorous process definitions to guide application of the complex structure of relati...
Aaron G. Cass, Leon J. Osterweil
ICDCS
1999
IEEE
15 years 10 months ago
Design Considerations for Distributed Caching on the Internet
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
Renu Tewari, Michael Dahlin, Harrick M. Vin, Jonat...
ISPD
1997
ACM
100views Hardware» more  ISPD 1997»
15 years 10 months ago
A pseudo-hierarchical methodology for high performance microprocessor design
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
A. Bertolet, K. Carpenter, Keith M. Carrig, Albert...
ATS
1996
IEEE
93views Hardware» more  ATS 1996»
15 years 10 months ago
Testable Design and Testing of MCMs Based on Multifrequency Scan
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...
Wang-Dauh Tseng, Kuochen Wang