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DFT
1998
IEEE
78views VLSI» more  DFT 1998»
15 years 11 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...
CHI
1993
ACM
15 years 11 months ago
A Wizard of Oz platform for the study of multimodal systems
The Wizard of Oz (WOz) technique is an experimental evaluation mechanism. It allows the observation of a user operating an apparently fully functioning system whose missing servic...
Daniel Salber, Joëlle Coutaz
EURODAC
1995
IEEE
128views VHDL» more  EURODAC 1995»
15 years 10 months ago
Closeness metrics for system-level functional partitioning
An important system design task is the partitioning of system functionality for implementation among multiple system components, including partitions among hardware and software c...
Frank Vahid, Daniel D. Gajski
ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
15 years 10 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Low-power techniques for network security processors
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu...