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ASPDAC
2006
ACM
134views Hardware» more  ASPDAC 2006»
16 years 24 days ago
Constraint driven I/O planning and placement for chip-package co-design
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
171
Voted
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
16 years 3 days ago
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update an...
Massimo Bombana, Francesco Bruschi
160
Voted
VLSID
2000
IEEE
95views VLSI» more  VLSID 2000»
15 years 11 months ago
Hierarchical Error Diagnosis Targeting RTL Circuits
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee...
MCI
2001
15 years 8 months ago
In a Strange Land: modelling and understanding cyberspace
: This paper begins with a long-term view of the development of cyberspace. This includes a brief examination of the worldview of a 16th-century mapmaker and over 4000 years of dev...
Alan J. Dix
NOCS
2010
IEEE
15 years 4 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...