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IWMM
2000
Springer
137views Hardware» more  IWMM 2000»
15 years 10 months ago
Cycles to Recycle: Garbage Collection on the IA-64
The IA-64, Intel's 64-bit instruction set architecture, exhibits a number of interesting architectural features. Here we consider those features as they relate to supporting ...
Richard L. Hudson, J. Eliot B. Moss, Sreenivas Sub...
LCN
2000
IEEE
15 years 10 months ago
Efficient Congestion Avoidance Mechanism
The nowadays Internet architecture is mainly based on unicast communications and best-effort service. However, the development of the Internet encouraged emerging services that ar...
Anca Dracinschi Sailer, Serge Fdida
PACS
2000
Springer
99views Hardware» more  PACS 2000»
15 years 10 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar
PACS
2000
Springer
118views Hardware» more  PACS 2000»
15 years 10 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
CAV
1997
Springer
102views Hardware» more  CAV 1997»
15 years 10 months ago
Efficient Model Checking Using Tabled Resolution
We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers. In particular,...
Y. S. Ramakrishna, C. R. Ramakrishnan, I. V. Ramak...
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