Sciweavers

1226 search results - page 79 / 246
» Designing systems-on-chip using cores
Sort
View
ASPLOS
2008
ACM
15 years 8 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ICASSP
2009
IEEE
16 years 1 months ago
Robust modeling of musical chord sequences using probabilistic N-grams
The modeling of music as a language is a core issue for a wide range of applications such as polyphonic music retrieval, automatic style identification, audio to symbolic music tr...
Ricardo Scholz, Emmanuel Vincent, Fréd&eacu...
SIGADA
2005
Springer
15 years 11 months ago
Experiences using SPARK in an undergraduate CS course
This paper describes experiences garnered while teaching a course on high integrity software using SPARK to a mix of junior and senior level undergraduates. The paper describes th...
Anthony S. Ruocco
PROCEDIA
2010
281views more  PROCEDIA 2010»
15 years 4 months ago
Introductory computational science using MATLAB and image processing
We describe a new course designed to introduce engineering students to computational thinking. One of the most significant challenges in teaching an introductory-level applied co...
D. Brian Larkins, William Harvey
DATE
2008
IEEE
77views Hardware» more  DATE 2008»
16 years 24 days ago
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
Feng Yuan, Lin Huang, Qiang Xu