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DAC
2006
ACM
16 years 7 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
IROS
2007
IEEE
114views Robotics» more  IROS 2007»
16 years 1 months ago
Synergistic 3D limit cycle walking of an anthropomorphic biped robot
— Human walking emerges from synergy of whole body dynamics: not only legs, but also a torso, arms, and a head are compliantly connected with each other by antagonistic muscles. ...
Koh Hosoda, Kenichi Narioka
ACSAC
2000
IEEE
15 years 11 months ago
Security Agility in Response to Intrusion Detection
Cooperative frameworks for intrusion detection and response exemplify a key area of today’s computer research: automating defenses against malicious attacks that increasingly ar...
M. Petkac, Lee Badger
CNSR
2010
IEEE
140views Communications» more  CNSR 2010»
15 years 10 months ago
Performance Evaluation of Using a Dynamic Shortest Path Algorithm in OLSRv2
—MANET routing protocols are designed to scale up to thousands of routers with frequent changes of the topology. In preference, MANET routing protocols should also support constr...
Ulrich Herberg
TVLSI
2008
197views more  TVLSI 2008»
15 years 6 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram