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DFT
2000
IEEE
105views VLSI» more  DFT 2000»
15 years 11 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
EWCBR
2008
Springer
15 years 8 months ago
Understanding Dubious Future Problems
Abstract. Being able to predict the performance of a Case-Based Reasoning(CBR) system against a set of future problems would provide invaluable information for design and maintenan...
Oguz Mülâyim, Josep Lluís Arcos
ICDE
2010
IEEE
206views Database» more  ICDE 2010»
15 years 8 months ago
HECATAEUS: Regulating Schema Evolution
HECATAEUS is an open-source software tool for enabling impact prediction, what-if analysis, and regulation of relational database schema evolution. We follow a graph theoretic appr...
George Papastefanatos, Panos Vassiliadis, Alkis Si...
VL
2008
IEEE
138views Visual Languages» more  VL 2008»
16 years 1 months ago
A case study of API redesign for improved usability
As software grows more complex, software developers’ productivity is increasingly defined by their ability to effectively reuse code. Even APIs (application programming interfac...
Jeffrey Stylos, Benjamin Graf, Daniela K. Busse, C...
TCAD
1998
125views more  TCAD 1998»
15 years 6 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...