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ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
15 years 12 months ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...
HIPEAC
2011
Springer
14 years 5 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
DAC
1996
ACM
15 years 10 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
ARC
2011
Springer
220views Hardware» more  ARC 2011»
15 years 29 days ago
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype
Abstract. In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation...
Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Os...
ESEC
1997
Springer
15 years 10 months ago
Executable Connectors: Towards Reusable Design Elements
The decomposition of a software application into components and connectors at the design stage has been promoted as a way to describe and reason about complex software architecture...
Stéphane Ducasse, Tamar Richner