Sciweavers

2945 search results - page 448 / 589
» Designing and Implementing Malicious Hardware
Sort
View
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
16 years 2 days ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
16 years 2 days ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 1 days ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
16 years 1 days ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
16 years 1 days ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich