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» Designing and Implementing Malicious Hardware
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ICS
2005
Tsinghua U.
15 years 12 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
AROBOTS
2007
129views more  AROBOTS 2007»
15 years 6 months ago
Behaviors for physical cooperation between robots for mobility improvement
— A team of small, low-cost robots instead of a single large, complex robot is useful in operations such as search and rescue, urban exploration etc. However, the performance of ...
Ashish Deshpande, Jonathan E. Luntz
DAC
2005
ACM
16 years 7 months ago
Word level predicate abstraction and refinement for verifying RTL verilog
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
16 years 19 days ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski