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ICASSP
2011
IEEE
14 years 10 months ago
A low-power implantable neuroprocessor on nano-FPGA for Brain Machine interface applications
This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interfa...
Fei Zhang, Mehdi Aghagolzadeh, Karim G. Oweiss
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 10 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
16 years 28 days ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
ECBS
2006
IEEE
158views Hardware» more  ECBS 2006»
16 years 16 days ago
Automated Translation of C/C++ Models into a Synchronous Formalism
For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system l...
Hamoudi Kalla, Jean-Pierre Talpin, David Berner, L...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 15 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...