Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
—Power management at any abstraction level is a key issue for many mobile multimedia and embedded applications. In this paper a design workflow to generate system-level power mo...
Patrick Bellasi, William Fornaciari, David Siorpae...
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang...