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ECBS
2007
IEEE
119views Hardware» more  ECBS 2007»
16 years 26 days ago
IPOG: A General Strategy for T-Way Software Testing
Most existing work on t-way testing has focused on 2-way (or pairwise) testing, which aims to detect faults caused by interactions between any two parameters. However, faults can ...
Yu Lei, Raghu Kacker, D. Richard Kuhn, Vadim Okun,...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 18 days ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 17 days ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
SAC
2006
ACM
16 years 14 days ago
Event-driven scheduling for dynamic workload scaling in uniprocessor embedded systems
Many embedded systems are designed to take timely reactions to the occurrences of interested scenarios. Sometimes transient overloads might be experienced due to hardware malfunct...
Li-Pin Chang
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
16 years 2 days ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...