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» Designing and Implementing Malicious Hardware
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ISCAS
2008
IEEE
103views Hardware» more  ISCAS 2008»
16 years 28 days ago
A low-power monolithically stacked 3D-TCAM
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...
Mingjie Lin, Jianying Luo, Yaling Ma
ISCAS
2008
IEEE
230views Hardware» more  ISCAS 2008»
16 years 28 days ago
Joint optimization of data hiding and video compression
— From copyright protection to error concealment, video data hiding has found usage in a great number of applications. Recently proposed applications such as privacy data preserv...
Jithendra K. Paruchuri, Sen-Ching S. Cheung
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
16 years 28 days ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
AHS
2007
IEEE
241views Hardware» more  AHS 2007»
16 years 27 days ago
Extreme Temperature Electronics - from Materials to Bio-inspired Adaptation
Biological systems have inherent mechanisms which ensure their adaptation and thus survival — preservation of functionality, despite extreme and varying environments. One such e...
Dragana Laketic, Pauline C. Haddow
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 26 days ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...