2945 search results - page 393 / 589 » Designing and Implementing Malicious Hardware |
141
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ISCAS
2005
IEEE
16 years 4 days ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
167
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ADAEUROPE
2005
Springer
15 years 8 months ago
2005
Springer
This paper presents the design and implementation of RT-EP (Real-Time Ethernet Protocol), which is a software-based token-passing Ethernet protocol for multipoint communications in...
165
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
264
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MEMOCODE
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the pa...
259
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OSN
2011
14 years 9 months ago
2011
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...