2945 search results - page 392 / 589 » Designing and Implementing Malicious Hardware |
179
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CVPR
1998
IEEE
16 years 8 months ago
1998
IEEE
We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA `s). We envision this ...
185
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
160
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
167
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ICSE
2003
IEEE-ACM
16 years 6 months ago
2003
IEEE-ACM
Some "non-' or "extra-functional" features, such as reliability, security, and tracing, defy modularization mechanisms in programming languages. This makes suc...
141
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FCCM
2007
IEEE
16 years 27 days ago
2007
IEEE
We present a domain-specific approach to generate highperformance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision....