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ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
16 years 1 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ISCAS
2007
IEEE
129views Hardware» more  ISCAS 2007»
16 years 27 days ago
ECC Processor with Low Die Size for RFID Applications
Abstract— This paper presents the design of a special purpose processor with Elliptic Curve Digital Signature Algorithm (ECDSA) functionality. This digital signature generation d...
Franz Fürbass, Johannes Wolkerstorfer
CODES
2005
IEEE
16 years 6 days ago
Conflict analysis in multiprocess synthesis for optimized system integration
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
Oliver Bringmann, Wolfgang Rosenstiel, Axel Sieben...
FPL
2005
Springer
140views Hardware» more  FPL 2005»
16 years 3 days ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
150
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FPL
2005
Springer
98views Hardware» more  FPL 2005»
16 years 3 days ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...