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FPL
2009
Springer
135views Hardware» more  FPL 2009»
15 years 11 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
CODES
2000
IEEE
15 years 11 months ago
Frequency interleaving as a codesign scheduling paradigm
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
170
Voted
DATE
1999
IEEE
134views Hardware» more  DATE 1999»
15 years 11 months ago
Verifying Imprecisely Working Arithmetic Circuits
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
Michaela Huhn, Klaus Schneider, Thomas Kropf, Geor...
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 10 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
15 years 10 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...