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» Designing and Implementing Malicious Hardware
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NCA
2006
IEEE
16 years 19 days ago
Full QoS Support with 2 VCs for Single-chip Switches
Current interconnection standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations ...
Alejandro Martínez, Francisco José A...
IPPS
2005
IEEE
16 years 6 days ago
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture
This paper presents the design and implementation of a thread virtual machine, called TNT (or TiNy-Threads) for the IBM Cyclops64 architecture (the latest Cyclops architecture tha...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
16 years 6 days ago
A low-power, 20-Gb/s continuous-time adaptive passive equalizer
—This paper describes a 20-Gb/s continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components. Passive equalizers offer the advantages of higher bandwidth an...
Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patri...
NIME
2004
Springer
154views Music» more  NIME 2004»
15 years 12 months ago
Synthesized Strings for String Players
A system is introduced that allows a string player to control a synthesis engine with the gestural skills he is used to. The implemented system is based on an electric viola and a...
Cornelius Poepel
EUROMICRO
2003
IEEE
15 years 12 months ago
Modelling the performance of CORBA using Layered Queueing Networks
One of the typical features of distributed systems is the heterogeneity of its components (e.g. geographical spreading and different platform architectures), leading to interopera...
Tom Verdickt, Bart Dhoedt, Frank Gielen, Piet Deme...