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ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 12 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ICC
2009
IEEE
122views Communications» more  ICC 2009»
16 years 1 months ago
Using Area Hierarchy for Multi-Resolution Storage and Search in Large Wireless Sensor Networks
—We consider multi-resolution storage, a technique for providing scalable adaptive data fidelity, necessary for many applications of large wireless sensor networks (WSNs). Altho...
Konrad Iwanicki, Maarten van Steen
IWMM
2009
Springer
125views Hardware» more  IWMM 2009»
16 years 1 months ago
Precise garbage collection for C
Magpie is a source-to-source transformation for C programs that enables precise garbage collection, where precise means that integers are not confused with pointers, and the liven...
Jon Rafkind, Adam Wick, John Regehr, Matthew Flatt
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
16 years 1 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...
FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
16 years 1 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...