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MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
15 years 11 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
MSS
2007
IEEE
129views Hardware» more  MSS 2007»
16 years 27 days ago
Cryptographic Security for a High-Performance Distributed File System
Storage systems are increasingly subject to attacks. Cryptographic file systems mitigate the danger of exposing data by using encryption and integrity protection methods and guar...
Roman Pletka, Christian Cachin
ARCS
2007
Springer
16 years 24 days ago
Architecture for Collaborative Business Items
Sensor network technology is pushing towards integration into the business world. By using sensor node hardware to augment real life business items it is possible to capture the wo...
Till Riedel, Christian Decker, Phillip Scholl, Alb...
ISCAS
2006
IEEE
105views Hardware» more  ISCAS 2006»
16 years 19 days ago
A CMOS contact imager for locating individual cells
— We describe the design of a contact imager for applications in lab-on-a-chip systems, such as sample preparation and manipulation and monitoring of cells. This is a challenging...
Honghao Ji, David Sander, A. Haas, Pamela Abshire
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
16 years 19 days ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman