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155
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ISQED
2002
IEEE
137views Hardware» more  ISQED 2002»
15 years 11 months ago
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
201
Voted
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 11 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
15 years 11 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
ICECCS
1998
IEEE
123views Hardware» more  ICECCS 1998»
15 years 11 months ago
Applying Slicing Technique to Software Architectures
Software architecture is receiving increasingly attention as a critical design level for software systems. As software architecture design resources (in the form of architectural ...
Jianjun Zhao
CODES
1996
IEEE
15 years 10 months ago
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...
Jean Paul Calvez, Dominique Heller, Olivier Pasqui...