2945 search results - page 355 / 589 » Designing and Implementing Malicious Hardware |
178
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ISCA
2000
IEEE
15 years 11 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
167
Voted
FPL
2005
Springer
16 years 5 days ago
2005
Springer
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is requir...
195
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
148
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
179
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...