Sciweavers

2945 search results - page 354 / 589
» Designing and Implementing Malicious Hardware
Sort
View
FCCM
1998
IEEE
119views VLSI» more  FCCM 1998»
15 years 11 months ago
Specifying and Compiling Applications for RaPiD
E cient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that...
Darren C. Cronquist, Paul Franklin, Stefan G. Berg...
JCC
2010
105views more  JCC 2010»
15 years 5 months ago
PAPER - Accelerating parallel evaluations of ROCS
Abstract: Modern graphics processing units (GPUs) are flexibly programmable and have peak computational throughput significantly faster than conventional CPUs. Herein, we describ...
Imran S. Haque, Vijay S. Pande
CHES
2011
Springer
254views Cryptology» more  CHES 2011»
14 years 6 months ago
Extractors against Side-Channel Attacks: Weak or Strong?
Randomness extractors are important tools in cryptography. Their goal is to compress a high-entropy source into a more uniform output. Beyond their theoretical interest, they have ...
Marcel Medwed, François-Xavier Standaert
FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 10 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
ICDE
2010
IEEE
248views Database» more  ICDE 2010»
16 years 6 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...