Sciweavers

2945 search results - page 348 / 589
» Designing and Implementing Malicious Hardware
Sort
View
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 8 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
16 years 1 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 10 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
ICIP
2006
IEEE
16 years 8 months ago
An Iris Recognition System Using Phase-Based Image Matching
This paper presents an implementation of iris recognition algorithm using phase-based image matching -- an image matching technique using phase components in 2D Discrete Fourier T...
Kazuyuki Miyazawa, Koichi Ito, Takafumi Aoki, Koji...
CAV
2009
Springer
212views Hardware» more  CAV 2009»
16 years 7 months ago
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
Susmit Jha, Rhishikesh Limaye, Sanjit A. Seshia