2945 search results - page 339 / 589 » Designing and Implementing Malicious Hardware |
169
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
145
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
126
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DSD
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...
162
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our ap...
168
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
The practical implementation of communication over power lines (PLC) using an Asymmetric Digital Subscriber Line (ADSL) front-end is discussed. Both PLC and ADSL modems are based ...