2945 search results - page 336 / 589 » Designing and Implementing Malicious Hardware |
135
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they...
133
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
209
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
183
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
123
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
ct In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of t...