2945 search results - page 332 / 589 » Designing and Implementing Malicious Hardware |
164
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ASYNC
2005
IEEE
16 years 9 days ago
2005
IEEE
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
184
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FPT
2005
IEEE
16 years 8 days ago
2005
IEEE
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
231
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DATE
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
139
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
146
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ICCAD
1998
IEEE
15 years 11 months ago
1998
IEEE
We survey the state-of-the-art in real-time operating systems (RTOSs) from the system synthesis point of view. RTOSs have a very long research history which provides important the...