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DAC
2003
ACM
16 years 7 months ago
Optimal integer delay budgeting on directed acyclic graphs
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...
ICCAD
2006
IEEE
106views Hardware» more  ICCAD 2006»
16 years 3 months ago
Wire density driven global routing for CMP variation and timing
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
16 years 1 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
16 years 1 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
167
Voted
FPL
2001
Springer
87views Hardware» more  FPL 2001»
15 years 11 months ago
Parameterized Function Evaluation for FPGAs
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry St...