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» Designing and Implementing Malicious Hardware
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FPL
2008
Springer
178views Hardware» more  FPL 2008»
15 years 8 months ago
High-speed regular expression matching engine using multi-character NFA
An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which a...
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kam...
MICRO
2006
IEEE
88views Hardware» more  MICRO 2006»
15 years 6 months ago
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback
Low-overhead checkpointing and rollback is a popular technique for fault recovery. While different approaches are possible, hardware-supported checkpointing and rollback at the ca...
Radu Teodorescu, Jun Nakano, Josep Torrellas
CHES
2003
Springer
104views Cryptology» more  CHES 2003»
15 years 12 months ago
Power-Analysis Attacks on an FPGA - First Experimental Results
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular, especially for rapid prototyping. For implementations of cryptographic algorithms, not only the speed and ...
Siddika Berna Örs, Elisabeth Oswald, Bart Pre...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
15 years 10 months ago
Automatically mapping applications to a self-reconfiguring platform
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt
CODES
2007
IEEE
16 years 1 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha