2945 search results - page 320 / 589 » Designing and Implementing Malicious Hardware |
220
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DFT
2005
IEEE
15 years 8 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
162
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DSD
2005
IEEE
16 years 9 days ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
179
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IJCNN
2000
IEEE
15 years 11 months ago
2000
IEEE
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
185
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FPL
2004
Springer
15 years 10 months ago
2004
Springer
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
156
Voted
FPL
2006
Springer
15 years 10 months ago
2006
Springer
The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions...