2945 search results - page 319 / 589 » Designing and Implementing Malicious Hardware |
178
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CODES
2008
IEEE
16 years 1 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
178
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MICRO
2008
IEEE
15 years 6 months ago
2008
IEEE
UAL PRIVATE MACHINE ABSTRACTION WOULD ALLOW SOFTWARE POLICIES TO EXPLICITLY MANAGE MICROARCHITECTURE RESOURCES. VPM POLICIES, IMPLEMENTED PRIMARILY IN SOFTWARE, TRANSLATE APPLICATI...
179
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FPL
2010
Springer
15 years 4 months ago
2010
Springer
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
165
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D desig...
131
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MICRO
2006
IEEE
16 years 21 days ago
2006
IEEE
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...