Sciweavers

2945 search results - page 310 / 589
» Designing and Implementing Malicious Hardware
Sort
View
ECBS
2004
IEEE
115views Hardware» more  ECBS 2004»
15 years 10 months ago
Supporting Evolutionary Development by Feature Models and Traceability Links
During their usage, software systems have to be changed constantly. If such changes are implemented in an incomplete or inconsistent way a loss of architectural quality will occur...
Matthias Riebisch
ICCAD
2010
IEEE
117views Hardware» more  ICCAD 2010»
15 years 4 months ago
A synthesis flow for digital signal processing with biomolecular reactions
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
15 years 4 months ago
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Abstract--As a replacement for the fast-fading GloballySynchronous model, we have defined a flexible design style called GRLS, for Globally-Ratiochronous, Locally-Synchronous, whic...
Jean-Michel Chabloz, Ahmed Hemani
CASES
2003
ACM
15 years 12 months ago
AES and the cryptonite crypto processor
CRYPTONITE is a programmable processor tailored to the needs of crypto algorithms. The design of CRYPTONITE was based on an in-depth application analysis in which standard crypto ...
Dino Oliva, Rainer Buchty, Nevin Heintze
ICCD
2004
IEEE
134views Hardware» more  ICCD 2004»
16 years 3 months ago
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Pallav Gupta, Rui Zhang, Niraj K. Jha